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| 1 mx25l12845e high performance serial flash specification mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428
2 contents features .................................................................................................................................................................. 5 general description ......................................................................................................................................... 7 table 1. additional features .............................................................................................................................. 7 pin configuration ................................................................................................................................................ 8 pin description ...................................................................................................................................................... 8 block diagram ....................................................................................................................................................... 9 data protection .................................................................................................................................................. 10 table 2. protected area sizes .......................................................................................................................... 11 table 3. 4k-bit secured otp defnition ............................................................................................................ 11 memory organization ............................................................................................................................................... 12 table 4. memory organization ........................................................................................................................ 12 device operation ................................................................................................................................................ 13 figure 1-1. serial modes supported (for normal serial mode) ............ ............................................................ 13 figure 1-2. serial modes supported (for double transfer rate serial read mode) .......................................... 13 command description ....................................................................................................................................... 14 table 5. command sets ................................................................................................................................... 14 (1) write enable (wren) ................................................................................................................................. 16 (2) write disable (wrdi) ............ ...................................................................................................................... 16 (3) read identifcation (rdid) .......................................................................................................................... 16 (4) read status register (rdsr) ........... ......................................................................................................... 17 (5) write status register (wrsr) ............ ........................................................................................................ 18 protection modes ............................................................................................................................................. 18 (6) read data bytes (read) ........................................................................................................................... 19 (7) read data bytes at higher speed (fast_read) ..................................................................................... 19 (8) fast double transfer rate read (fastdtrd) .......................................................................................... 19 (9) 2 x i/o read mode (2read) ........... ........................................................................................................... 19 (10) 2 x i/o double transfer rate read mode (2dtrd) ........... ...................................................................... 20 (11) 4 x i/o read mode (4read) ............ ......................................................................................................... 20 (12) 4 x i/o double transfer rate read mode (4dtrd) ........... ...................................................................... 21 (13) sector erase (se) ..................................................................................................................................... 21 (14) block erase (be) ....................................................................................................................................... 22 (15) block erase (be32k) ................................................................................................................................ 22 (16) chip erase (ce) ........................................................................................................................................ 22 (17) page program (pp) ................................................................................................................................... 23 (18) 4 x i/o page program (4pp) ..................................................................................................................... 23 program/erase flow(1) with read array data ................................................................................................... 24 program/erase flow(2) without read array data .............................................................................................. 25 (19) continuously program mode (cp mode) .................................................................................................. 26 (20) parallel mode (highly recommended for production throughputs increasing) .......................................... 26 (21) deep power-down (dp) ............................................................................................................................ 27 (22) release from deep power-down (rdp), read electronic signature (res) ............................................ 27 (23) read electronic manufacturer id & device id (rems), (rems2), (rems4), (rems4d) ....................... 27 table 6. id defnitions ..................................................................................................................................... 28 (24) enter secured otp (enso) ..................................................................................................................... 28 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 3 (25) exit secured otp (exso) ........................................................................................................................ 28 (26) read security register (rdscur) .......................................................................................................... 28 security register defnition .............................................................................................................................. 29 (27) write security register (wrscur) .......................................................................................................... 29 (28) write protection selection (wpsel) ......................................................................................................... 30 bp and srwd if wpsel=0 ............................................................................................................................. 30 the individual block lock mode is effective after setting wpsel=1 ................................................................. 31 wpsel flow .................................................................................................................................................... 32 (29) single block lock/unlock protection (sblk/sbulk) ............ ................................................................... 33 block lock flow ........... .................................................................................................................................... 33 block unlock flow ............................................................................................................................................ 34 (30) read block lock status (rdblock) ....................................................................................................... 35 (31) gang block lock/unlock (gblk/gbulk) ................................................................................................. 35 (32) clear sr fail flags (clsr) ............ .......................................................................................................... 35 (33) read sfdp mode (rdsfdp) ............ ....................................................................................................... 36 read serial flash discoverable parameter (rdsfdp) sequence .................................................................. 36 table a. signature and parameter identifcation data values ......................................................................... 37 table b. parameter table (0): jedec flash parameter tables ....................................................................... 38 table c. parameter table (1): macronix flash parameter tables ..................................................................... 40 power-on state ................................................................................................................................................... 42 electrical specifications .............................................................................................................................. 43 absolute maximum ratings ................................................................................................................... 43 figure 2. maximum negative overshoot waveform ........................................................................................ 43 capacitance ta = 25c, f = 1.0 mhz ........................................................................................................... 43 figure 3. maximum positive overshoot waveform ........... ............................................................................... 43 figure 4. input test waveforms and measurement level ............ ................................................ 44 figure 5. output loading ......................................................................................................................... 44 table 7. dc characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v ~ 3.6v) . 45 table 8. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v ~ 3.6v) 46 timing analysis ........................................................................................................................................................ 48 figure 6. serial input timing ............................................................................................................................ 48 figure 7. output timing .................................................................................................................................... 48 figure 8. serial input timing for double transfer rate mode .......................................................................... 49 figure 9. serial output timing for double transfer rate mode ........... ............................................................ 49 figure 10. wp# setup timing and hold timing during wrsr when srwd=1 ............ ................................... 50 figure 11. write enable (wren) sequence (command 06) ........................................................................... 50 figure 12. write disable (wrdi) sequence (command 04) ............ ................................................................ 50 figure 13. read identifcation (rdid) sequence (command 9f) .................................................................... 51 figure 14. read status register (rdsr) sequence (command 05) ........... ................................................... 51 figure 15. write status register (wrsr) sequence (command 01) ............ ................................................. 51 figure 16. read data bytes (read) sequence (command 03) .................................................................... 52 figure 17. read at higher speed (fast_read) sequence (command 0b) ........... ..................................... 52 figure 18. fast dt read (fastdtrd) sequence (command 0d) ............ ..................................................... 52 figure 19. 2 x i/o read mode sequence (command bb) ............................................................................... 53 figure 20. fast dual i/o dt read (2dtrd) sequence (command bd) ......................................................... 53 figure 21. 4 x i/o read mode sequence (command eb) ............................................................................... 54 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 4 figure 22. 4 x i/o read enhance performance mode sequence (command eb) .......................................... 54 figure 23. fast quad i/o dt read (4dtrd) sequence (command ed) ........................................................ 55 figure 24. fast quad i/o dt read (4dtrd) enhance performance sequence (command ed) ................... 55 figure 25. sector erase (se) sequence (command 20) ................................................................................ 56 figure 26. block erase (be/be32k) sequence (command d8/52) ................................................................ 56 figure 27. chip erase (ce) sequence (command 60 or c7) ......................................................................... 56 figure 28. page program (pp) sequence (command 02) .............................................................................. 57 figure 29. 4 x i/o page program (4pp) sequence (command 38) ............ .................................................... 57 figure 30. continously program (cp) mode sequence with hardware detection (command ad) ............ ..... 58 figure 31-1. enter parallel mode (enplm) sequence (command 55) .......................................................... 59 figure 31-2. exit parallel mode (explm) sequence (command 45) ........... .................................................. 59 figure 31-3. parallel mode read identifcation (parallel rdid) sequence (command 9f) ........................... 59 figure 31-4. parallel mode read electronic manufacturer & device id (parallel rems) sequence (command 90) ........... ......................................................................................................................................................... 60 figure 31-5. parallel mode release from deep power-down (rdp) and read electronic signature (res) sequence ......................................................................................................................................................... 60 figure 31-6. parallel mode read array (parallel read) sequence (command 03) ...................................... 61 figure 31-7. parallel mode page program (parallel pp) sequence (command 02) ...................................... 61 figure 32. deep power-down (dp) sequence (command b9) ....................................................................... 61 figure 33. read electronic signature (res) sequence (command ab) ........................................................ 62 figure 34. release from deep power-down (rdp) sequence (command ab) ............................................. 62 figure 35. read electronic manufacturer & device id (rems) sequence (command 90 or ef or df or cf) .. 63 figure 36. write protection selection (wpsel) sequence (command 68) .................................................... 63 figure 37. single block lock/unlock protection (sblk/sbulk) sequence (command 36/39) ..................... 64 figure 38. read block protection lock status (rdblock) sequence (command 3c) ................................ 64 figure 39. gang block lock/unlock (gblk/gbulk) sequence (command 7e/98) ...................................... 64 figure 40. power-up timing ............................................................................................................................. 65 table 9. power-up timing ........... .................................................................................................................... 65 initial delivery state ............................................................................................................................... 65 operating conditions ....................................................................................................................................... 66 figure 41. ac timing at device power-up ....................................................................................................... 66 figure 42. power-down sequence .................................................................................................................. 67 erase and programming performance .................................................................................................... 68 data retention .................................................................................................................................................... 68 latch-up characteristics .............................................................................................................................. 68 ordering information ...................................................................................................................................... 69 part name description ..................................................................................................................................... 70 package information ........................................................................................................................................ 71 revision history ................................................................................................................................................. 73 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 5 128m-bit [x 1/x 2/x 4] cmos mxsmio ? (serial multi i/o) flash memory features general 6huldo3hulskhudo,qwhuidfhfrpsdwleoh0rghdqg0rgh ? 128mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two i/o mode) structure or 33,554,432 x 4 bits (four i/o mode) structure (txdo6hfwruzlwk.ewhhdfk - any sector can be erased individually (txdoorfnzlwk.ewhhdfk - any block can be erased individually (txdoorfnzlwk.ewhhdfk - any block can be erased individually 3rzhu6xsso2shudwlrq - 2.7 to 3.6 volt for read, erase, and program operations /dwfkxssurwhfwhgwrpiurp9wr9ff9 performance ljk3huirupdqfh 9&& a9 - normal read - 50mhz - fast read (normal serial mode) - 1 i/o: 104mhz with 8 dummy cycles - 2 i/o: 70mhz with 4 dummy cycles - 4 i/o: 70mhz with 6 dummy cycles - fast read (double transfer rate mode ) - 1 i/o: 50mhz with 6 dummy cycles - 2 i/o: 50mhz with 6 dummy cycles - 4 i/o: 50mhz with 8 dummy cycles - fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - byte program time: 9us (typical) - continuously program mode (automatically increase address under word program mode) - fast erase time: 60ms (typ.)/sector (4k-byte per sector) ; 0.7s(typ.) /block (64k-byte per block); 80s(typ.) /chip /rz3rzhu&rqxpswlrq - low active read current: 19ma(max.) at 104mhz, 15ma(max.) at 66mhz and 10ma(max.) at 33mhz - low active programming current: 25ma (max.) - low active erase current: 25ma (max.) - low standby current: 100ua (max.) - deep power down current: 40ua (max.) 7slfdohudhsurjudpffoh software features ,qsxwdwd)rupdw - 1-byte command code mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 6 ? advanced security features - bp0-bp3 block group protect - flexible individual block protect when otp wpsel=1 - additional 4k bits secured otp for unique identifer ? auto erase and auto program algorithms - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse width (any page to be programed should have page in the erased state frst.) ? status register feature electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems, rems2, rems4 and rems4d commands for 1-byte manufacturer id and 1-byte device id support serial flash discoverable parameters (sfdp) mode hardware features sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o mode and 4 x i/o mode ? so/sio1/po7 - serial data output or serial data input/output for 2 x i/o mode and 4 x i/o mode or parallel data ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o mode ? nc/sio3 - nc pin or serial data input/output for 4 x i/o mode ? po0~po6 - for parallel mode data (only 128mb provide parallel mode) ? package - 16-pin sop (300mil) - 8-wson (8x6mm) - all devices are rohs compliant and halogen-free mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 7 table 1. additional features general description mx25l12845e is 134,217,728 bits serial flash memory, which is confgured as 16,777,216 x 8 internally. when it is in two or four i/o mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. the mx25l12845e features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. mx25l12845e provides high performance read mode, which may latch address and data on both rising and falling edge of clock. by using this high performance read mode, the data throughput may be doubling. moreover, the per - formance may reach direct code execution, the ram size of the system may be reduced and further saving system cost. mx25l12845e, mxsmio (serial multi i/o) fash memory, provides sequential read operation on the whole chip and multi-i/o features. when it is in dual i/o mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in quad i/o mode, the si pin, so pin, wp# pin and nc pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data input/output. parallel mode is also provided in this device. it features 8 bit input/output for increasing throughputs. this feature is recommeded to be used for factory produc - tion purpose. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fed page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, or word basis. continuously program mode and erase command are executed on 4k-byte sector, 32k- byte/64k-byte block, or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via the wip bit. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 100ua dc cur - rent. the mx25l12845e utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. additional features part name protection and security read performance flexible or individual block (or sector) protection 4k-bit secured otp 1 i/o read (104 mhz) 2 i/o read (70 mhz) 4 i/o read (70 mhz) 1 i/o dt read (50 mhz) 2 i/o dt read (50 mhz) 4 i/o dt read (50 mhz) 8 i/o parallel mode (6 mhz) mx25l12845e v v v v v v v v v (note 1) additional features part name identifer res (command: ab hex) rems (command: 90 hex) rems2 (command: ef hex) rems4 (command: df hex) rems4d (command: cf hex) rdid (command: 9f hex) mx25l12845e 17 (hex) c2 17 (hex) c2 17 (hex) c2 17 (hex) c2 17 (hex) c2 20 18 (hex) note 1: only mx25l12845e provide parallel mode. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 8 pin configuration 16-pin sop (300mil) 1 2 3 4 5 6 7 8 nc/sio3 vcc nc po2 po1 po0 cs# so/sio1/po7 16 15 14 13 12 11 10 9 sclk si/sio0 po6 po5 po4 po3 gnd wp#/sio2 8-wson (8x6mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc nc/sio3 sclk si/sio0 pin description symbol description cs# chip select si/sio0 serial data input (for 1xi/o)/ serial data input & output (for 2xi/o or 4xi/o mode) so/sio1/ po7 serial data output (for 1xi/o)/serial data input & output (for 2xi/o or 4xi/o mode) / parallel data output/input sclk clock input wp#/sio2 write protection: connect to gnd or serial data input & output (for 4xi/o mode) nc/sio3 nc pin (not connect) or serial data input & output (for 4xi/o mode) vcc + 3.3v power supply gnd ground po0~po6 parallel data output/input (po0~po6 can be connected to nc in serial mode) nc no connection mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 9 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 nc/sio3 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 10 data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before is - suing other commands to change data. the wel bit will return to reset stage under following situations: - power-up - w rite disable (wrdi) command completion - w rite status register (wrsr) command completion - page program (pp , 4pp) command completion - continuously program m ode (cp) instruction completion - sector erase (se) command completion - block erase (be, be32k) command completion - chip erase (ce) comma nd completion - single block lock/unlock (sblk/sbulk) instruction completion - gang block lock/unlock (gblk/gbulk) instruction completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic sig - nature command (res). i. block lock protection - the software protected mode (spm) uses (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as table of " protected area sizes ", the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of " protect- ed area sizes ". - the hardware protected mode (hpm) uses wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and srwd bit. if the system goes into four i/o mode, the feature of hpm will be disabled. - mx25l12845e provides individual block (or sector) write protect & unprotect. user may enter the mode with wpsel command and conduct individual block (or sector) write protect with sblk instruction, or sbulk for individual block (or sector) unprotect. under the mode, user may conduct whole chip (all blocks) protect with gblk instruction and unlock the whole chip with gbulk instruction. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 11 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting de - vice unique serial number - which may be set by factory or system maker. please refer to table 3. 4k-bit se - cured otp defnition . - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of " security register defnition " for secu - rity register bit defnition and table of " 4k-bit secured otp defnition " for address range defnition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 4k-bit se - cured otp mode, array access is not allowed. table 3. 4k-bit secured otp defnition table 2. protected area sizes note: the device is ready to accept a chip erase instruction if, and only if, all block protect (bp3, bp2, bp1, bp0) are 0. address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a status bit protection area bp3 bp2 bp1 bp0 128mb 0 0 0 0 0 (none) 0 0 0 1 1 (2 blocks, block 254th-255th) 0 0 1 0 2 (4 blocks, block 252nd-255th) 0 0 1 1 3 (8 blocks, block 248th-255th) 0 1 0 0 4 (16 blocks, block 240th-255th) 0 1 0 1 5 (32 blocks, block 224th-255th) 0 1 1 0 6 (64 blocks, block 192nd-255th) 0 1 1 1 7 (128 blocks, block 128th-255th) 1 0 0 0 8 (256 blocks, all) 1 0 0 1 9 (256 blocks, all) 1 0 1 0 10 (256 blocks, all) 1 0 1 1 11 (256 blocks, all) 1 1 0 0 12 (256 blocks, all) 1 1 0 1 13 (256 blocks, all) 1 1 1 0 14 (256 blocks, all) 1 1 1 1 15 (256 blocks, all) mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 12 memory organization table 4. memory organization block(32k-byte) sector 4095 fff000h ffffffh ? 4088 ff8000h ff8fffh 4087 ff7000h ff7fffh ? 4080 ff0000h ff0fffh 4079 fef000h feffffh ? 4072 fe8000h fe8fffh 4071 fe7000h fe7fffh ? 4064 fe0000h fe0fffh 4063 fdf000h fdffffh ? 4056 fd8000h fd8fffh 4055 fd7000h fd7fffh ? 4048 fd0000h fd0fffh 47 02f000h 02ffffh ? 40 028000h 028fffh 39 027000h 027fffh ? 32 020000h 020fffh 31 01f000h 01ffffh ? 24 018000h 018fffh 23 017000h 017fffh ? 16 010000h 010fffh 15 00f000h 00ffffh ? 8 008000h 008fffh 7 007000h 007fffh ? 0 000000h 000fffh 508 507 506 address range 511 510 509 individual block lock/unlock unit:64k-byte individual 16 sectors lock/unlock unit:4k-byte individual block lock/unlock unit:64k-byte individual block lock/unlock unit:64k-byte block(64k-byte) 253 2 1 0 255 254 0 5 4 3 2 1 individual 16 sectors lock/unlock unit:4k-byte mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 13 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended opera - tion. 2. when incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next cs# falling edge. in standby mode, so pin of the device is high-z. 3. when correct command is inputted to this device, it enters active mode and remains in active mode until next cs# rising edge. 4. for standard single data rate serial mode, input data is latched on the rising edge of serial clock (sclk) and data is shifted out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 1-1 . for high performance (double transfer rate read serial mode), data is latched on both rising and falling edge of clock and data shifts out on both rising and falling edge of clock as figure 1-2 . 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, rdsfdp, 2read, 4read,fastdtrd, 2dtrd, 4dtrd, rdblock, res, rems, rems2, rems4, and rems4d the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, be32k, hpm, ce, pp, cp, 4pp, rdp, dp, wpsel, sblk, sbulk, gblk, gbulk, enso, exso, wrscur, enplm, explm and clsr the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. while a w rite status register, program, or erase operation is in progress, access to the memory array is ne - glected and will not affect the current operation of write status register, program, erase. figure 1-1. serial modes supported (for normal serial mode) note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. figure 1-2. serial modes supported (for double transfer rate serial read mode) sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb sclk msb cpha data in data in data out data out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 14 command description table 5. command sets command (byte) wren (write enable) wrdi (write disable) rdid (read identifcation) rdsr (read status register) wrsr (write status register) fastdtrd (fast dt read) 2dtrd (dual i/o dt read) 4dtrd (quad i/o dt read) command (hex) 06 04 9f 05 01 0d bd ed input cycles data(8) add(12) add(6) add(3) dummy cycles 6 6 1+7 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out the values of the status register to write new values to the status register n bytes read out (double transfer rate) until cs# goes high n bytes read out (double transfer rate) by 2xi/ o until cs# goes high n bytes read out (double transfer rate) by 4xi/ o until cs# goes high command (byte) read (read data) fast read (fast read data) rdsfdp (read sfdp) 2read (2 x i/o read command) note1 4read (4 x i/o read command) 4pp (quad page program) se (sector erase) be (block erase 64kb) command (hex) 03 0b 5a bb eb 38 20 d8 input cycles add(24) add(24) add(24) add(12) add(6) add(6)+ data(512) add(24) add(24) dummy cycles 8 8 4 2+4 action n bytes read out until cs# goes high n bytes read out until cs# goes high read sfdp mode n bytes read out by 2 x i/ o until cs# goes high n bytes read out by 4 x i/ o until cs# goes high quad input to program the selected page to erase the selected sector to erase the selected 64kb block command (byte) be 32k (block erase 32kb) ce (chip erase) pp (page program) cp (continuously program mode) dp (deep power down) rdp (release from deep power down) res (read electronic id) rems (read electronic manufacturer & device id) command (hex) 52 60 or c7 02 ad b9 ab ab 90 input cycles add(24) add(24)+ data(2048) add(24)+ data(16) add(24) dummy cycles 24 action to erase the selected 32kb block to erase whole chip to program the selected page continously program whole chip, the address is automatically increase enters deep power down mode release from deep power down mode to read out 1-byte device id output the manufacturer id & device id mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 15 notes : 1. it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hidden mode. 2: in individual block write protection mode, all blocks/sectors is locked as defualt. command (byte) be 32k (block erase 32kb) rems4 (read id for 4x i/o mode) rems4d (read id for 4x i/o dt mode) enso (enter secured otp) exso (exit secured otp) rdscur (read security register) wrscur (write security register) command (hex) 52 df cf b1 c1 2b 2f input cycles add(24) add(24) add(24) dummy cycles action to erase the selected 32kb block output the manufact- urer id & device id output the manufact- urer id & device id to enter the 4k- bit secured otp mode to exit the 4k- bit secured otp mode to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be updated) command (byte) enplm (enter parallel mode) explm (exit parallel mode) clsr (clear sr fail flags) hpm (high performance enable mode) wpsel (write protection selection) sblk (single block lock) *note 2 sbulk (single block unlock) command (hex) 55 45 30 a3 68 36 39 input cycles add(24) add(24) dummy cycles action 8xi/o parallel programming mode to exit 8xi/ o parallel programming mode clear security register bit 6 and bit 5 quad i/o high performance mode to enter and enable individal block protect mode individual block (64k-byte) or sector (4k-byte) write protect individual block (64k-byte) or sector (4k-byte) unprotect command (byte) rdblock (block protect read) gblk (gang block lock) gbulk (gang block unlock) command (hex) 3c 7e 98 input cycles add(24) dummy cycles action read individual block or sector write protect status whole chip write protect whole chip unprotect mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 16 (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, cp, se, be, be32k, ce, wrsr, sblk, sbulk, gblk and gbulk, which are intended to change the device con - tent, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction code cs# goes high. (please refer to figure 11 ) (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low send ing wrdi instruction code cs# goes high. (please refer to figure 12 ) the wel bit is reset by following situations: - power-up - w rite disable (wrdi) instruction completion - w rite status register (wrsr) instruction completion - page program (pp , 4pp) instruction completion - sector erase (se) instruction completion - block erase (be, be32k) instruction completion - chip erase (ce) instruction completion - continuously program mode (cp) instruction completion - single block lock/unlock (sblk/sbulk) instruction completion - gang block lock/unlock (gblk/gbulk) instruction completion (3) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is 20(hex) as the frst-byte device id, and the individual device id of second-byte id are listed as table of " id defnitions ". (please refer to table 6) the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code 24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. (please refer to figure 13 ) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 17 (4) read status register (rdsr) the rdsr instruction is for reading status register. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so (please refer to figure 14 ). the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to "1", which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. the program/erase command will be ignored and will reset wel bit if it is applied to a protected memory area. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in table 2) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase (ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed). qe bit. the quad enable (qe) bit, non-volatile bit, while it is "0" (factory default), it performs non-quad and wp# is enable. while qe is "1", it performs quad i/o mode and wp# is disabled. in the other word, if the system goes into four i/o mode (qe=1), the feature of hpm will be disabled. srwd bit. the status register write disable (srwd) bit, non-volatile bit, default value is "0". srwd bit is operat - ed together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. status register note: see the table 2 "protected area size" in page 11. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1= quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 18 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the pro - tected area of memory (as shown in table 2 ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on si cs# goes high. (please refer to figure 15 ) the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. protection modes note: as defined by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 2. as the table above showing, the summary of the software protected mode (spm) and hardware protected mode (hpm): software protected mode (spm): - when sr wd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when sr wd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software pro - tected mode (spm) hardware protected mode (hpm): - when sr wd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system goes into four i/o mode, the feature of hpm will be disabled. mode status register condition wp# and srwd bit status memory software protection mode(spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 19 (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code3-byte address on si data out on so to end read operation can use cs# to high at any time during data out. (please refer to fig - ure 16) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes lowsending fast_read instruction code3-byte address on si 1-dummy byte (default) address on sidata out on so to end fast_read operation can use cs# to high at any time during data out. (please refer to figure 17 ) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (8) fast double transfer rate read (fastdtrd) the fastdtrd instruction is for doubling reading data out, signals are triggered on both rising and falling edge of clock. the address is latched on both rising and falling edge of sclk, and data of each bit shifts out on both rising and falling edge of sclk at a maximum frequency fc2. the 2-bit address can be latched-in at one clock, and 2-bit data can be read out at one clock, which means one bit at rising edge of clock, the other bit at falling edge of clock. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fastdtrd instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fastdtrd instruction is: cs# goes low sending fastdtrd instruction code (1bit per clock) 3-byte address on si (2-bit per clock) 6-dummy clocks (default) on si data out on so (2-bit per clock) to end fastdtrd operation can use cs# to high at any time during data out. (please refer to figure 18 ) while program/erase/write status register cycle is in progress, fastdtrd instruction is rejected without any im - pact on the program/erase/write status register current cycle. (9) 2 x i/o read mode (2read) the 2read instruction enables double transfer rate of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 20 mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruc - tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address in - terleave on sio1 & sio0 4-bit dummy cycle on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (please refer to figure 19 for 2 x i/o read mode timing waveform). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. (10) 2 x i/o double transfer rate read mode (2dtrd) the 2dtrd instruction enables double transfer rate throughput on dual i/o of serial flash in read mode. the ad - dress (interleave on dual i/o pins) is latched on both rising and falling edge of sclk, and data (interleave on dual i/o pins) shift out on both rising and falling edge of sclk at a maximum frequency ft2. the 4-bit address can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at rising edge of clock, the other two bits at falling edge of clock. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2dtrd instruction. the address counter rolls over to 0 when the highest ad - dress has been reached. once writing 2dtrd instruction, the following address/dummy/ data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 2dtrd instruction is: cs# goes low sending 2dtrd instruction (1-bit per clock) 24- bit address interleave on sio1 & sio0 (4-bit per clock) 6-bit dummy clocks on sio1 & sio0 data out inter - leave on sio1 & sio0 (4-bit per clock) to end 2dtrd operation can use cs# to high at any time during data out (please refer to figure 20 for 2 x i/o double transfer rate read mode timing waveform ). while program/erase/write status register cycle is in progress, 2dtrd instruction is rejected without any impact on the program/erase/write status register current cycle. (11) 4 x i/o read mode (4read) the 4read instruction enables quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the ad - dress counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the fol - lowing address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address in - terleave on sio3, sio2, sio1 & sio0 6 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out (please refer to figure 21 for 4 x i/o read mode timing waveform ). another sequence of issuing 4read instruction especially useful in random access is : cs# goes low sending 4 read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 21 p[7:0] 4 dummy cycles data out still cs# goes high cs# goes low (reduce 4 read instruction) 24-bit ran - dom access address (please refer to figure 22 for 4x i/o read enhance performance mode timing waveform ). in the performance-enhancing mode (notes of figure. 22 ), p[7:4] must be toggling with p[3:0]; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh, 00h, aah or 55h. these commands will reset the performance enhance mode. and afterwards cs# is raised and then lowered, the system then will return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. (12) 4 x i/o double transfer rate read mode (4dtrd) the 4dtrd instruction enables double transfer rate throughput on quad i/o of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4dtrd instruction. the address (interleave on 4 i/o pins) is latched on both rising and falling edge of sclk, and data (interleave on 4 i/o pins) shift out on both rising and falling edge of sclk at a maximum frequency fq2. the 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at fall - ing edge of clock. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4dtrd instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 4dtrd instruc - tion, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit. the sequence of issuing 4dtrd instruction is: cs# goes low sending 4dtrd instruction (1-bit per clock) 24- bit address interleave on sio3, sio2, sio1 & sio0 (8-bit per clock) 8 dummy clocks data out interleave on sio3, sio2, sio1 & sio0 (8-bit per clock) to end 4dtrd operation can use cs# to high at any time during data out (please refer to figure 23 for 4 x i/o read mode double transfer rate timing waveform ). another sequence of issuing enhanced mode of 4dtrd instruction especially useful in random access is: cs# goes low sending 4dtrd instruction (1-bit per clock) 3-bytes ad dress interleave on sio3, sio2, sio1 & sio0 (8-bit per clock) performance enhance toggling bit p[7:0] 7 dummy clocks data out(8-bit per clock) still cs# goes high cs# goes low (eliminate 4 read instruction) 24-bit random access address (please refer to figure 24 for 4x i/o double transfer rate read enhance performance mode timing waveform ). while program/erase/write status register cycle is in progress, 4dtrd instruction is rejected without any impact on the program/erase/write status register current cycle. (13) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 4 ) is a valid address for sector erase (se) in - struction. the cs# must go high exactly at the byte boundary (the least signifcant bit of the address been latched- in); otherwise, the instruction will be rejected and not executed. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. (please refer to figure 25 ) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets during the tse timing, and clears when sector erase cycle is completed, and the write enable latch (wel) bit is cleared. if the sector is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit still be reset. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 22 (14) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 4 ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. (please refer to figure 26 ) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets during the tbe timing, and clears when block erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit still be reset. (15) block erase (be32k) the block erase (be32) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be32). any address of the block (see table 4) is a valid address for block erase (be32) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32 instruction is: cs# goes low sending be32 instruction code 3-byte address on si cs# goes high. (please refer to figure 26 ) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the block erase cycle is in progress. the wip sets during the tbe tim - ing, and clears when block erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit still be reset. (16) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must be executed to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low send ing ce instruction code cs# goes high. (please refer to figure 27 ) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the chip erase cycle is in progress. the wip sets during the tce tim - ing, and clears when chip erase cycle is completed, and the write enable latch (wel) bit is cleared. if the chip is protected the chip erase (ce) instruction will not be executed, but wel will be reset. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 23 (17) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7-a0 (the eight least signifcant address bits) should be set to 0. the last address byte (the 8 least signifcant ad - dress bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the re - quest page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page . the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. ( please refer to figure 28 ) the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the page program cycle is in progress. the wip sets during the tpp timing, and clears when page program cycle is completed, and the write enable latch (wel) bit is cleared. if the page is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit will still be reset. (18) 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3, which can raise programer performance and and the effectiveness of application of lower clock less than 20mhz. for system with faster clock, the quad page program cannot provide more performance, because the required internal page program time is far more than the time data fows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0] cs# goes high. (please refer to figure 29 ) if the page is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit will still be reset. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 24 the program/erase function instruction function fow is as follows: program/erase flow(1) with read array data wren command program/erase command write program data/address (write erase address) rdsr command read array data (same address of pgm/ers) program/erase successfully yes yes program/erase fail no no start program/erase completed verify ok? wip=0? program/erase another block? yes no rdsr command* yes wren=1? no * * issue rdsr to check bp[3:0]. * if wpsel=1, issue rdblock to check the block status. clsr(30h) command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 25 program/erase flow(2) without read array data wren command program/erase command write program data/address (write erase address) rdsr command rdscur command program/erase successfully yes no program/erase fail yes p_fail/e_fail=1? wip=0? program/erase another block? yes no rdsr command* yes wren=1? no start no program/erase completed * issue rdsr to check bp[3:0]. * if wpsel=1, issue rdblock to check the block status. clsr(30h) command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 26 (19) continuously program mode (cp mode) the cp mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. the continuously program (cp) instruction is for multiple byte program to flash. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the continuously program (cp) instruction. cs# requires to go high before cp instruction is executing. after cp instruction and address input, two bytes of data is input sequentially from msb(bit7) to lsb(bit0). the frst byte data will be programmed to the initial address range with a0=0 and second byte data with a0=1. if only one byte data is input, the cp mode will not process. if more than two bytes data are input, the additional data will be ignored and only two byte data are valid. any byte to be programmed should be in the erase state (ff) frst. it will not roll over during the cp mode, once the last unpro - tected address has been reached, the chip will exit cp mode and reset write enable latch bit (wel) as "0" and cp mode bit as "0". please check the wip bit status if it is not in write progress before entering next valid instruction. during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr command (05 hex), and rdscur command (2b hex). and the wrdi command is valid after completion of a cp programming cy - cle, which means the wip bit=0. the sequence of issuing cp instruction is : cs# goes low sending cp instruction code 3-byte address on si pin two data bytes on si cs# goes high to low sending cp instruction and then continue two data bytes are programmed cs# goes high to low till last desired two data bytes are programmed cs# goes high to low sending wrdi (write disable) instruction to end cp mode send rdsr instruction to verify if cp mode word program ends, or send rdscur to check bit4 to verify if cp mode ends. (please refer to figure 30 of cp mode timing waveform ) two methods to detect the completion of a program cycle during cp mode: 1) software method-i: by checking wip bit of status register to detect the completion of cp mode. 2) software method-ii: by waiting for a tbp time out to determine if it may load next valid command or not. if the page is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit will still be reset. (20) parallel mode (highly recommended for production throughputs increasing) the parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. the parallel mode requires 55h command code, after writing the parallel mode command and then cs# going high, after that, the memory can be available to accept rdid/res & rems/read/pp command as the normal writing command procedure. to exit parallel mode, it requires 45h command code, or power-off/on sequence. the sequence of issuing paralle mode instruction is : cs# goes lowsending parallel mode codecs# goes high ( please refer to figure 31-1 , and refer to figure 31-2 ~31-7 for other parallel mode). a. for normal write command (by si), no ef fect b. under parallel mode, the fastest access clock freq. will be changed to 6mhz (sclk pin clock freq.) c. for parallel mode, the tv will be changed to 70ns. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 27 (21) deep power-down (dp) the deep power-down (dp) instruction is for setting the device to minimum power consumption (the standby cur - rent is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, the device is only in standby mode, not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes low sending dp instruction code cs# goes high. (please refer to figure 32 ) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (22) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is completed by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the standby power mode. if the device was not previously in the deep power-down mode, the transition to the standby power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by tres2, and chip se - lect (cs#) must remain high for at least tres2(max), as specifed in table 8 . once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions . this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro - gram/erase/write cycles in progress. the sequence is shown as figure 33 , 34. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is for releasing from deep power-down mode. (23) read electronic manufacturer id & device id (rems), (rems2), (rems4), (rems4d) the rems, rems2, rems4 and rems4d instruction provides both the jedec assigned manufacturer id and the specifc device id. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h", "cfh", "dfh" or "efh" fol - lowed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 34. the device id values are listed in table of id defnitions . if the one-byte address is initially set to 01h, then the de - vice id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 28 table 6. id defnitions command type mx25l12845e rdid manufacturer id memory type memory density c2 20 18 res electronic id 17 rems/rems2/rems4/rems4d manufacturer id device id c2 17 (24) enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. while the device is in 4k-bit se - cured otp mode, array access is not available. the additional 4k-bit secured otp is independent from main array and may be used to store unique serial number for system identifer. after entering the secured otp mode, follow standard read or program procedure to read out the data or update data. the secured otp data cannot be updat - ed again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. please note that wrsr/wrscur/wpsel/sblk/gblk/sbulk/gbulk/ce/be/se/be32k commands are not ac - ceptable during the access of secure otp region. once security otp is lock down, only read related commands are valid. (25) exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. (26) read security register (rdscur) the rdscur instruction is for reading the value of security register. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low sending rdscur instruction security regis - ter data out on so cs# goes high. the defnition of the security register is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for cus - tomer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be updated any more. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 29 (27) write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the se - cured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. security register defnition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpsel e_fail p_fail continuously program mode (cp mode) x x ldso (lock-down 4k-bit se- cured otp) 4k-bit secured otp 0=normal wp mode 1=individual wp mode (default=0) 0=normal erase succeed 1=indicate erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) 0=normal program mode 1=cp mode (default=0) reserved reserved 0 = not lockdown 1 = lock- down (cannot program/ erase otp) 0 = nonfactory lock 1 = factory lock non-volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit otp read only read only read only read only read only otp read only continuously program mode( cp mode) bit. the continuously program mode bit indicates the status of cp mode, "0" indicates not in cp mode; "1" indicates in cp mode. program fail flag bit. while a program failure happened, the program fail flag bit would be set. this bit will also be set when the user attempts to program a protected main memory region or a locked otp region. this bit can in - dicate whether one or more of program operations fail, and can be reset by command clsr (30h) erase fail flag bit. while a erase failure happened, the erase fail flag bit would be set. this bit will also be set when the user attempts to erase a protected main memory region or a locked otp region. this bit can indicate whether one or more of erase operations fail, and can be reset by command clsr (30h) write protection select bit. the write protection select bit indicates that wpsel has been executed successfully. once this bit has been set (wpsel=1), all the blocks or sectors will be write-protected after the power-on every time. once wpsel has been set, it cannot be changed again, which means it's only for individual wp mode. under the individual block protection mode (wpsel=1), hardware protection is performed by driving wp#=0. once wp#=0 all array blocks/sectors are protected regardless of the contents of sram lock bits. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 30 (28) write protection selection (wpsel) there are two write protection methods, (1) bp protection mode (2) individual block protection mode. if wpsel=0, fash is under bp protection mode . if wpsel=1, fash is under individual block protection mode. the default value of wpsel is 0. wpsel command can be used to set wpsel=1. please note that wpsel is an otp bit. once wpsel is set to 1, there is no chance to recovery wpsel back to 0. if the fash is put on bp mode, the indi - vidual block protection mode is disabled. contrarily, if fash is on the individual block protection mode, the bp mode is disabled. every time after the system is powered-on, the security register bit 7 is checked. if wpsel=1, all the blocks and sectors will be write protected by default. user may only unlock the blocks or sectors via sbulk and gbulk instructions. program or erase functions can only be operated after the unlock instruction is executed. bp protection mode, wpsel=0: array is protected by bp3~bp0 and bp3~bp0 bits are protected by srwd=1 and wp#=0, where srwd is bit 7 of status register that can be set by wrsr command. individual block protection mode, wpsel=1: blocks are individually protected by their own sram lock bits which are set to 1 after power up. sbulk and sblk command can set sram lock bit to 0 and 1. when the system accepts and executes wpsel instruction, the bit 7 in security register will be set. it will activate sblk, sbulk, rdblock, gblk, gbulk etc instructions to conduct block lock protection and replace the original software protect mode (spm) use (bp3~bp0) indicated block meth - ods.under the individual block protection mode (wpsel=1), hardware protection is performed by driving wp#=0. once wp#=0 all array blocks/sectors are protected regardless of the contents of sram lock bits. the sequence of issuing wpsel instruction is: cs# goes low sending wpsel instruction to enter the individual block protect mode cs# goes high. wpsel instruction function fow is as follows: 64kb 64kb . . . 64kb 64kb bp3 bp2 bp1 bp0 srwd w p# pin bp and srwd if wpsel=0 (1) bp3~bp0 is used to defne the protection group region. (the protected area size see table 2) (2) srwd=1 and wp#=0 is used to protect bp3~bp0. in this case, srwd and bp3~bp0 of status register bits can not be changed by wrsr mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 31 the individual block lock mode is effective after setting wpsel=1 64kb 4kb 64kb 4kb sram sram sram 4kb 4kb sram uniform 64kb bl oc ks sram sram 4kb sram sbulk / sblk / gbulk / gblk / rdblock ?? ? ? ? ? ? ? bottom 4kbx16 sectors top 4kbx16 sectors ? power-up: all sram bits=1 (all blocks are default protected). all array cannot be programmed/erased ? sblk/sbulk(36h/39h): - sblk(36h) : set sram bit=1 (protect) : array can not be programmed/erased - sbulk(39h): set sram bit=0 (unprotect): array can be programmed/erased - all top 4kbx16 sectors and bottom 4kbx16 sectors and other 64kb uniform blocks can be protected and unprotect ed with sram bits individually by sblk/sbulk command set. ? gblk/ gbulk(7eh/98h): - gblk(7eh): set all sram bits=1, the whole chip is protected and cannot be programmed/erased. - gbulk(98h): set all sram bits=0, the whole chip is unprotected and can be programmed/erased. - all sectors and blocks sram bits of the whole chip can be protected and unprotected at one time by gblk/gbulk command set. ? rdblock(3ch): - use rdblock mode to check the sram bits status after sbulk /sblk/gbulk/gblk command set. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 32 wpsel flow rdscur(2bh) command rdsr command rdscur(2bh) command wpsel set successfully yes yes wpsel set fail no start wpsel=1? wip=0? no wpsel disable, block protected by bp[3:0] yes no wpsel=1? wpsel(68h) command wpsel enable. block protected by individual lock (sblk, sbulk, ? etc). mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 33 block lock flow rdscur(2bh) command start wren command sblk command ( 36h + 24bit address ) rdsr command rdblock command ( 3ch + 24bit address ) block lock successfully yes yes block lock fail no data = ffh ? wip=0? lock another block? block lock completed no yes no no yes wpsel=1? wpsel command (29) single block lock/unlock protection (sblk/sbulk) these instructions are only effective after wpsel was executed. the sblk instruction is for write protection a spec - ifed block(or sector) of memory, using a23-a16 or (a23-a12) address bits to assign a 64kbyte block (or 4k bytes sector) to be protected as read only. the sbulk instruction will cancel the block (or sector) write protection state. this feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (gbulk). the wren (write enable) instruction is required before issuing sblk/sbulk instruction. the sequence of issuing sblk/sbulk instruction is: cs# goes low send sblk/sbulk (36h/39h) instruction send 3 address bytes assign one block (or sector) to be protected on si pin cs# goes high. (please refer to fig- ure 37) the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. sblk/sbulk instruction function fow is as follows: mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 34 block unlock flow wren command rdscur(2bh) command sbulk command ( 39h + 24bit address ) rdsr command yes wip=0? unlock another block? yes no no yes unlock block completed? start wpsel=1? wpsel command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 35 (30) read block lock status (rdblock) this instruction is only effective after wpsel was executed. the rdblock instruction is for reading the status of protection lock of a specifed block(or sector), using a23-a16 (or a23-a12) address bits to assign a 64k bytes block (4k bytes sector) and read protection lock status bit which the frst byte of read-out cycle. the status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. the status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. the sequence of issuing rdblock instruction is: cs# goes low send rdblock (3ch) instruction send 3 ad - dress bytes to assign one block on si pin read block's protection lock status bit on so pin cs# goes high. (please refer to figure 38 ) (31) gang block lock/unlock (gblk/gbulk) these instructions are only effective after wpsel was executed. the gblk/gbulk instruction is for enable/disable the lock protection block of the whole chip. the wren (write enable) instruction is required before issuing gblk/gbulk instruction. the sequence of issuing gblk/gbulk instruction is: cs# goes low send gblk/gbulk (7eh/98h) instruction cs# goes high. (please refer to figure 39 ) the cs# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. (32) clear sr fail flags (clsr) the clsr instruction is for resetting the program/erase fail flag bit of security register. it should be executed be - fore program/erase another block during programming/erasing fow without read array data. the sequence of issuing clsr instruction is: cs# goes low send clsr instruction code cs# goes high. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 36 (33) read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a standard of jedec. jesd216. v1.0. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 37 table a. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers start from 01h 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 38 table b. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction requested for writing to volatile status registers 0: nonvolatitle status bit 1: volatitle status bit (bp status register bit) 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 0b b8h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 1b (1-2-2) fast read 0=not support 1=support 20 1b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 0b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 07ffffffh (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0100b 44h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 0000b 00h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 ffh ffh mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 39 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ch 04:00 0 0000b 00h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 0xffh 0xffh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3eh 20:16 0 0100b 04h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support 1=support 40h 00 0b eeh unused 03:01 111b (4-4-4) fast read 0=not support 1=support 04 0b unused 07:05 111b unused 43h:41h 31:08 0xffh 0xffh unused 45h:44h 15:00 0xffh 0xffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 46h 20:16 0 000b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 0xffh 0xffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 4ah 20:16 0 0000b 00h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (4-4-4) fast read opcode 4bh 31:24 ffh ffh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 40 table c. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 36h 00h 36h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 23:16 31:24 00h 27h 00h 27h hw reset# pin 0=not support 1=support 65h:64h 00 0b 4ff4h hw hold# pin 0=not support 1=support 01 0b deep power down mode 0=not support 1=support 02 1b sw reset 0=not support 1=support 03 0b sw reset opcode reset enable (66h) should be issued before reset command 11:04 1111 1111b (ffh) program suspend/resume 0=not support 1=support 12 0b erase suspend/resume 0=not support 1=support 13 0b unused 14 1b wrap-around read mode 0=not support 1=support 15 0b wrap-around read mode opcode 66h 23:16 ffh ffh wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 ffh ffh individual block lock 0=not support 1=support 6bh:68h 00 1b c8d9h individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 0b individual block lock opcode 09:02 0011 0110b (36h) individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 0b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11b unused 31:16 0xffh 0xffh unused 6fh:6ch 31:00 0xffh 0xffh mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 41 note 1: h/b is hexadecimal or binary . note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h note 6: 0xffh means all data is blank ("1b"). mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 42 power-on state the device is at the following states after power-up: - standby mode ( please n ote it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage until the vcc reaches the following levels: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the fgure of "power-up timing ". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf) mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 43 notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see figure 2, 3. absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 1.0 mhz figure 2. maximum negative overshoot waveform vss vss-2.0v 20ns 20ns 20ns figure 3. maximum positive overshoot waveform vcc + 2.0v vcc 20ns 20ns 20ns symbol parameter min. typ. max. unit conditions cin input capacitance 20 pf vin = 0v cout output capacitance 20 pf vout = 0v rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 4.0v mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 44 figure 5. output loading device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30/15pf including jig capacitance figure 4. input test waveforms and measurement level ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 45 table 7. dc characteristics (temperature = -40 c to 85c for industrial grade, vcc = 2.7v ~ 3.6v) notes : 1. t ypical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. t ypical value is calculated by simulation. symbol parameter notes min. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout=vcc or gnd isb1 vcc standby current 1 100 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 40 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 22 ma fq=70mhz (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 19 ma f=104mhz sclk=0.1vcc/0.9vcc, so=open 17 ma ft=70mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 15 ma f=66mhz sclk=0.1vcc/0.9vcc, so=open 10 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 25 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 25 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.8 v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma; iol = 140ua for parallel mode voh output high voltage vcc-0.2 v ioh = -100ua; ioh = 65ua for parallel mode mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 46 table 8. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v ~ 3.6v) symbol alt. parameter min. max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr serial d.c. 104 mhz parallel 6 mhz frsclk fr clock frequency for read instructions 50 mhz ftsclk ft clock frequency for 2read instructions 70 mhz fq clock frequency for 4read instructions vcc=2.7v-3.6v 70 mhz vcc=3.0v-3.6v 85 mhz fc2 clock frequency for fastdtrd instructions 50 mhz ft2 clock frequency for 2dtrd instructions 50 mhz fq2 clock frequency for 4dtrd instructions 50 mhz f4pp clock frequency for 4pp (quad page program) 20 mhz tch (1) tclh clock high time serial 4.5 (fast_read) ns serial 9 (read) ns parallel 30 ns tcl (1) tcll clock low time serial 4.5 (fast_read) ns serial 9 (read) ns parallel 30 ns tclch (2) clock rise time (3) (peak to peak) serial 0.1 v/ns parallel 0.25 v/ns tchcl (2) clock fall time (3) (peak to peak) serial 0.1 v/ns parallel 0.25 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time serial 2 ns parallel 10 ns tchdx tdh data in hold time serial 5 ns parallel 10 ns tchsh cs# active hold time (relative to sclk) serial 5 ns parallel 30 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl (3) tcsh cs# deselect time read 15 ns write/erase/ program 50 ns tshqz (2) tdis output disable time 2.7v-3.6v serial 10 ns 3.0v-3.6v serial 8 ns parallel 20 ns tclqv tv clock low to output valid vcc=2.7v~3.6v loading: 15pf 1 i/o 9 ns 2 i/o & 4 i/o 9.5 ns loading: 30pf 2 i/o & 4 i/o 12 ns parallel 70 ns mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 47 notes: 1. tch + tcl must be greater than or equal to 1/ fc. 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a wrsr instruction when srwd is set at 1. symbol alt. parameter min. typ. max. unit tclqv2 tv2 clock low to output valid (dtr mode) vcc=2.7v~3.6v, loading: 15pf 1 i/o, 2 i/o & 4 i/o 9.5 ns tclqx tho output hold time 2 ns twhsl write protect setup time 20 ns tshwl write protect hold time 100 ns tdp (2) cs# high to deep power-down mode 10 us tres1 (2) cs# high to standby mode without electronic signature read 100 us tres2 (2) cs# high to standby mode with electronic signature read 100 us tw write status register cycle time 40 100 ms tbp byte-program 9 300 us tpp page program cycle time 1.4 5 ms tse sector erase cycle time (4kb) 60 300 ms tbe block erase cycle time (32kb) 0.5 2 s tbe block erase cycle time (64kb) 0.7 2 s tce chip erase cycle time 80 200 s twps write protection selection time 1 ms twsr write security register time 1 ms mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 48 figure 6. serial input timing figure 7. output timing timing analysis sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 49 figure 8. serial input timing for double transfer rate mode figure 9. serial output timing for double transfer rate mode sclk si cs# msb so tdvch tdvch high-z lsb tslch tchdx tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv2 tclqx tclqv2 tclqv2 sclk so cs# si mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 50 figure 10. wp# setup timing and hold timing during wrsr when srwd=1 figure 11. write enable (wren) sequence (command 06) figure 12. write disable (wrdi) sequence (command 04) 21 34567 high-z 0 04 sclk si cs# so command 21 34567 high-z 0 06 command sclk si cs# so high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 51 figure 13. read identifcation (rdid) sequence (command 9f) 21 3456789 10 11 12 13 14 15 0 manufacturer identification high-z msb device identification msb d7 d15 d14 d13 d6 d5 d3 d3 d2 d2 d1 d1 d0 d0 d4 16 17 18 28 29 30 31 sclk si cs# so 9f command figure 14. read status register (rdsr) sequence (command 05) figure 15. write status register (wrsr) sequence (command 01) 21 3456789 10 11 12 13 14 15 command 0 d7 d6 d5 d4 d3 d2 d1 d0 status register out high-z msb sclk si cs# so 05 21 3456789 10 11 12 13 14 15 status register in 0 msb sclk si cs# so 01 high-z command d7 d6 d5 d4 d3 d2 d1 d0 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 52 figure 16. read data bytes (read) sequence (command 03) sclk si cs# so 21 3456789 10 28 29 30 31 32 33 34 35 36 37 38 data out 1 24 add cycles 0 msb msb msb 39 data out 2 03 high-z command d7 a23 a22 a21 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 figure 17. read at higher speed (fast_read) sequence (command 0b) 21 3456789 10 28 29 30 31 high-z 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 8 dummy cycles msb 47 35 sclk si cs# so 0b command d7 d7 d6 d5 d4 d3 d2 d1 d0 data out 1 data out 2 24 add cycles a23 a22 a21 a3 a2 a1 a0 figure 18. fast dt read (fastdtrd) sequence (command 0d) 19 25 26 27 28 29 8 7 0 0d si/sio0 so/sio1 cs# a23 a22 a1 a0 sclk d7 d6 d5 d4 d3 d2 d1 d7d0 command 12 add cycles 6 dummy cycles data out 1 data out 2 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 53 figure 19. 2 x i/o read mode sequence (command bb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 18 19 20 bb(hex) 21 22 23 24 25 26 27 28 29 p0 p2 p1 p3 d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 12 add cycle 4 dummy cycle a22 a20 a2 a0 a3 a1 a23 a21 data out 1 data out 2 note: si/sio0 or so/sio1 should be kept "0h" or "fh" in the frst two dummy cycles. in other words, p2=p0 or p3=p1 is necessary. figure 20. fast dual i/o dt read (2dtrd) sequence (command bd) 0 7 8 13 14 19 20 21 bd si/sio0 so/sio1 cs# a22 a20 a23 a21 a2 a0 a3 a1 p2 p0 p3 p1 sclk d6 d4 d2 d0 d6 d4 d2 d0 d6 d7 d5 d3 d1 d7 d5 d3 d1 d7 22 23 data out 1 data out 2 command 6 add cycles 6 dummy cycles note: si/sio0 or so/sio1 should be kept "0h" or "fh" in the frst two dummy cycles. in other words, p2=p0 or p3=p1 is necessary. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 54 figure 21. 4 x i/o read mode sequence (command eb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 eb p4 p0 p5 p1 p6 p2 p7 p3 15 16 17 18 19 20 21 22 high impedance wp#/sio2 high impedance nc/sio3 4 dummy cycles performance enhance indicator (note1, 2) d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d5 d6 d7 a20 a21 a22 a23 a16 a17 a18 a19 a12 a13 a14 a15 a8 a9 a10 a11 a4 a5 a6 a7 a0 a1 a2 a3 command 6 add cycles data out 1 data out 2 data out 3 notes: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) will result in entering the performance enhance mode. figure 22. 4 x i/o read enhance performance mode sequence (command eb) high impedance 6 7 8 10 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 eb p4 p0 p5 p1 p6 p2 p7 p3 15 16 n+1 n+7 n+9 n+13 17 18 19 20 21 22 23 high impedance wp#/sio2 high impedance nc/sio3 4 dummy cycles 4 dummy cycles performance enhance indicator (note) p4 p0 p5 p1 p6 p2 p7 p3 performance enhance indicator (note) command 6 add cycles 6 add a20 a21 a22 a23 a16 a17 a18 a19 a12 a13 a14 a15 a8 a9 a10 a11 a4 a5 a6 a7 a0 a1 a2 a3 a20 a21 a22 a23 a0 a1 a2 a3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 data out 1 data out 2 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d5 d6 d7 data out 1 data out 2 data out 3 cycles notes: 1. performance enhance mode: if p7p3 & p6p2 & p5p1 & p4p0 (t oggling), ex: a5, 5a, f0, 0f. 2. reset the performance enhance mode: if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 55, 00, ff. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 55 figure 23. fast quad i/o dt read (4dtrd) sequence (command ed) notes: 1. hi-impedance is inhibited for this clock cycle. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) will result in entering the performance enhance mode. 7 dummy cycles ed si/sio0 so/sio1 cs# wp#/sio2 nc/sio3 sclk p4 p0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d6 d5 d4 1 cycle performance enhance indicator (note1,2) 0 7 8 9 10 11 18 19 20 a0 a20 a16 a17a21 a18a22 a19a23 a4 a1a5 a2a6 a3 a7 command 3 add cycles p7 p6 p5 p1 p2 p3 figure 24. fast quad i/o dt read (4dtrd) enhance performance sequence (command ed) 7 dummy cycles data out 1 data out 2 command ed (hex) si/sio0 so/sio1 cs# wp#/sio2 nc/sio3 sclk a0 a1 a2 a3 a20 3 add cycles 0 7 8 9 10 11 18 19 20 a16 a17a21 a18a22 a19a23 a4 a5 a6 a7 p4 p5 p6 p7 p0 p1 p2 p3 d7 d3 d6 d2 d5 d1 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 performance enhance indicator (note) 1 cycle 7 dummy cycles data out 1 data out 2 3 add cycles d7 d3 d6 d2 d5 d1 d4 d7 d6 d5 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 performance enhance indicator (note) 1 cycle a0 a1 a2 a3 a20 a16 a17a21 a18a22 a19a23 a4 a5 a6 a7 p4 p5 p6 p7 p0 p1 p2 p3 note: performance enhance, if p7p3 & p6p2 & p5p1 & p4p0 (toggle) mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 56 figure 25. sector erase (se) sequence (command 20) figure 26. block erase (be/be32k) sequence (command d8/52) 21 3456789 29 30 31 0 msb sclk cs# si 20 command 24 add cycles a23 a22 a2 a1 a0 ? ? 21 3456789 29 30 31 0 msb sclk cs# si d8/52 command 24 add cycles a23 a22 a2 a1 a0 b b figure 27. chip erase (ce) sequence (command 60 or c7) 21 34567 0 60 or c7 sclk si cs# command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 57 figure 28. page program (pp) sequence (command 02) figure 29. 4 x i/o page program (4pp) sequence (command 38) 21 3456789 10 28 29 30 31 32 33 34 35 36 37 38 24 add cycles 0 data byte 1 39 data byte 256 2079 2078 2077 2076 2075 2074 2073 2072 msb msb sclk cs# si 02 command d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a23 a22 a21 a3 a2 a1 a0 a20 a16 a12 a8 a4 a0 a21 a17 a13 a9 a5 a1 a22 a18 a14 a10 a6 a2 a23 a19 a15 a11 a7 a3 21 3456789 6 add cycles data byte 1 data byte 2 data byte 256 0 sclk cs# si/sio0 so/sio1 nc/sio3 wp#/sio2 38 command 10 11 12 13 14 15 16 17 524 525 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 58 figure 30. continously program (cp) mode sequence with hardware detection (command ad) notes: (1) during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr command (05 hex), and rdscur command (2b hex). (2) once an internal program ming operation begins, cs# goes low will drive the status on the so pin and cs# goes high will return the so pin to tri-state. (3) t o end the cp mode, either reaching the highest unprotected address or sending write disable (wrdi) com - mand (04 hex) may achieve it and then it is recommended to send rdsr command (05 hex) to verify if cp mode is ended. cs# sclk 0 1 6 7 8 9 si command ad (hex) 30 31 31 s0 high impedance 32 47 48 status (2) data in 24-bit address byte 0, byte1 0 1 valid command (1) data in byte n-1, byte n 6 7 8 20 21 22 23 0 04 (hex) 24 7 0 7 05 (hex) 8 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 59 figure 31-1. enter parallel mode (enplm) sequence (command 55) 21 34567 high-z 0 55 command sclk si cs# so figure 31-2. exit parallel mode (explm) sequence (command 45) 21 34567 high-z 0 45 sclk si cs# so command figure 31-3. parallel mode read identifcation (parallel rdid) sequence (command 9f) 20 1 3 4 5 6 7 8 9 10 manufacturer identification high-z device identification sclk si cs# po7~0 9f command note: there are 3 data bytes which would be output sequentially for manufacturer and device id 1'st byte (memory type) and device id 2'nd byte (memory density). mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 60 figure 31-4. parallel mode read electronic manufacturer & device id (parallel rems) sequence (command 90) 21 3456789 10 0 sclk si cs# po7~0 90 high-z command 24 add cycles a23 a22 a21 a2a3 a1 a0 31 32 33 3028 29 manufacturer identification device identification note: a0=0 will output the manufacturer id frst and a0=1 will output device id frst. a1~a23 don't care. figure 31-5. parallel mode release from deep power-down (rdp) and read electronic signature (res) se - quence 21 3456789 10 28 29 30 31 32 33 34 35 36 37 38 high impedance electronic signature out instruction 0 byte output stand-by mode deep power-down mode t res2 sclk cs# si po7~0 24 add cycles ab a23 a22 a21 a3 a2 a1 a0 note: under parallel mode, the fastest access clock freg. will be changed to 6mhz(sclk pin clock freg.) t o release from deep power-down mode and read id in parallel mode, which requires a parallel mode com - mand (55h) before the read status register command. t o exit parallel mode, it requires a (45h) command or power-off/on sequence. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 61 figure 31-6. parallel mode read array (parallel read) sequence (command 03) high-z 24 add cycles msb sclk cs# si po7~0 03 command a23 a22 a21 a3 a2 a1 a0 n 333231302928109876543210 n-1 ? d0~d7 byte 1 d0~d7 byte 2 d0~d7 byte n d0~d7 byte n-1 figure 31-7. parallel mode page program (parallel pp) sequence (command 02) sclk si cs# po7~0 24 add cycles msb msb 02 high-z command data byte1 data byte255 data byte256 data byte2 data byte3 a23 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 286 287 a22 a21 a3 a2 a1 a0 figure 32. deep power-down (dp) sequence (command b9) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 62 figure 34. release from deep power-down (rdp) sequence (command ab) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command figure 33. read electronic signature (res) sequence (command ab) 21 3456789 10 28 29 30 31 32 33 34 35 36 37 38 high-z electronic signature out 24 add cycles 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command a23 a22 a21 a3 a2 a1 a0 ? d7 d6 d5 d4 d3 d2 d1 d0 39 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 63 notes: 1. a0=0 will output the manufacturer id frst and a0=1 will output device id frst. a1~a23 is don't care. 2. instruction is either 90(hex) or ef(hex) or df(hex) or cf(hex). figure 35. read electronic manufacturer & device id (rems) sequence (command 90 or ef or df or cf) 21 3456789 10 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 manufacturer id msb device id msb msb 47 35 sclk si cs# so 90 high-z command 24 add cycles a23 a22 a21 a2a3 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 313028 29 figure 36. write protection selection (wpsel) sequence (command 68) 21 34567 0 68 sclk si cs# command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 64 figure 37. single block lock/unlock protection (sblk/sbulk) sequence (command 36/39) figure 38. read block protection lock status (rdblock) sequence (command 3c) 24 bit address cycles 21 3456789 29 30 31 0 msb sclk cs# si 36/39 command a23 a22 a2 a1 a0 21 3456789 10 28 29 30 31 32 33 34 35 36 37 38 high-z block protection lock status out 24 add cycles 0 msb msb sclk cs# si so 3c command a23 a22 a21 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 39 figure 39. gang block lock/unlock (gblk/gbulk) sequence (command 7e/98) 21 34567 0 7e/98 sclk si cs# command mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 65 figure 40. power-up timing note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: the parameter is characterized only. table 9. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 300 us mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 66 notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v operating conditions at device power-up and power-down ac timing illustrated in figure 41 and figure 42 are for the supply voltages and the control signals at device power- up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 41. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 67 figure 42. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 68 erase and programming performance notes: 1. t ypical program and erase time assumes the following conditions: 25c, 3.3v, and checkerboard pattern. 2. under worst conditions of 85c and 2.7v . 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. latch-up characteristics min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. parameter typ. (1) max. (2) unit write status register cycle time 40 100 ms sector erase time (4kb) 60 300 ms block erase time (64kb) 0.7 2 s block erase time (32kb) 0.5 2 s chip erase time 80 200 s byte program time (via page program command) 9 300 us page program time 1.4 5 ms erase/program cycle 100,000 cycles data retention parameter condition min. max. unit data retention 55?c 20 years mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 69 ordering information part no. clock (mhz) temperature package remark mx25l12845emi-10g 104 -40c~85c 16-sop (300mil) rohs compliant mx25l12845ezni-10g 104 -40c~85c 8-wson (8x6mm) rohs compliant mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 70 part name description mx 25 l m i temperature range: i: industrial (-40 c to 85 c) package: m: 300mil 16-sop zn: 8x6mm 8-wson density & mode: 12845e: 128mb standard type type: l: 3v device: 25: serial flash 12845e 10 g option: g: rohs compliant & halogen-free speed: 10: 104mhz mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 71 package information mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 72 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 73 revision history revision no. description page date 1.0 1. removed "preliminary" p5 ma y/19/2009 2. merge mx25l6445e and mx25l12845e together all 3. add cfi mode content p37 4. align waveform format all 5. modify tch/tcl value, from rev0.06 tch/tcl=5.5ns p43,45 to rev1.0 tc h/tcl(fast_read/read)=4.5/9ns 6. change com mand table format p15,16 7. added " data retention" condition p66 8. modifed se ctor erase time from 90ms to 60ms p5,43,46, p66 9. modifed 12 8mb chip erase time (max) from 512s to 200s p46,66 1.1 1. added 128m 8-wson epn p67 jul/16/2009 2. change rd cfi command from a5 to 5a p16,37 1.2 1. added dmc code content table p37~39 oct/21/2009 2. removed mx25l12845ezni-10g advanced information remark p69 3. changed th e naming "cfi mode" as "dmc mode" all 1.3 1. corrected error p8,43,44,54 apr/01/2010 p68 2. added wording "e.g. vcc and cs# ramp up simultaneously" p67 3. modifed low active read and standby current consumption p5,43~44,69 and deep power down current consumption 4. deleted par allel mode condition p43 5. modifed tab le of " read dmc mode (rddmc)" p37~39 6. added " input test waveforms and measurement level " p42 7. modifed tslch, tshch from 8ns to 5ns p45,47 1.4 1. removed dmc sequence description & content table p6,14,16,37 jul/14/2010 2. revised low active read current spec p5 3. revised table 7-1 and table 7-2 p40~41 1.5 1. removed mx25l6445e information from the previous combined all aug/15/201 1 version of mx25l6445e/mx25l12845e 2. modifed description for rohs compliance p6,63,64 3. revised figure 18. fast dt read (fastdtrd) sequence p46,47,49 figure 20. fast dual i/o dt read (2dtrd) sequence ; figure 23. fast quad i/o dt read (4dtrd) sequence ; and figure 24. fast quad i/o dt read (4dtrd) enhance performance . 4. corrected ilo test conditions in table 7 p39 5. revised storage temperature p37 6. revised cp mode completion method descriptions p26 7. revised device operation descriptions p13 1.6 1. added quad i/o read frequency: 85mhz@vcc=3.0v~3.6v p40 sep/13/201 1 1.7 1. revised the description in the individual block lock mode p31 oct/05/201 1 1.8 1. modifed input capacitance & output capacitance p43 feb/10/2012 2. modifed figure 42. power-down sequence p67 3. changed or dering information format p69 4. added read sfdp (rdsfdp) mode p6,13,14, p36~41,46 1.9 1. modifed absolute maximum ratings table p43 sep/06/2013 mx25l12845e rev. 1.9, sep. 06, 2013 p/n: pm1428 mx25l12845e 74 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2009~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com |
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